Thermal testing of integrated logic circuits (IC), or power electronic devices provides signatures of defects and failure modes in these complex structures where non-uniform temperature distribution and hot spots are generated. By using a lock-in transient thermal imaging technique, we observed the heating history due to a complex startup sequence in a series of 2D temperature maps over time. This is not achievable by conventional IR imaging or liquid crystal thermography. A microscope with 5x objective enabled us to view an area of 2.5 mm x 2.5 mm with 2.4 μm/pixel. We observed a regular powering up sequence of the IC from a cold start. Approximately 30 seconds of averaging (repeating the same sequence) was carried out to improve the temperature resolution and image quality. Depending on the load change in time, the thermal history of the localized hotspots was identified. When the irregular electric signal is detected from a sample, the thermal information in time helps to determine the location of a potential failure even when it is very small. We also demonstrated that the time response information is also applicable to the structural thermal analysis using network identification by deconvolution.